The present invention relates to a method for driving a display and a drive circuit for a display.
An electronic device, such as a notebook type personal computer, employs a liquid crystal display, which is provided with a multiple gray scale display function. A driver IC, which drives the display, includes a gray scale selection circuit for selecting a gray scale voltage in accordance with an image signal. The gray scale selection circuit includes a multiplicity of gates and occupies a large portion of the driver IC. Thus, to reduce the size of the driver IC, it is required that the number of gates in the gray scale selection circuit be decreased.
In the liquid crystal display of the prior art, the pixel voltage applied to each pixel cell of a liquid crystal display panel (LCD panel) is controlled to realize a multiple gray scale display. FIG. 1 is a schematic diagram showing a prior art example of a driver IC 1 for driving an LCD panel.
A logic section 2, which serves as a controller, is arranged in the middle of the driver IC 1. A data latch circuit 3, a gray scale selection circuit 4, and an operational amplifier 5 are configured on each of the left and right sides of the logic section 2. The gray scale selection circuit 4 includes a plurality of gates and occupies about thirty percent of the entire chip. For example, in a driver IC that drives eight bit data lines with 256 gray scales, a driver IC having 480 outputs would have to have a total of 983,040 gates on the entire chip.
FIG. 2 is a schematic diagram of the gray scale selection circuit 4 in the prior art. The gray scale selection circuit 4 is connected to a series-connected circuit 2a, which includes ladder resistors R, and receives a divisional voltage generated by the ladder resistors R. The ladder resistors R divide a reference voltage into, for example, 256. In other words, the divisional voltages generated by the ladder resistors R correspond to 256 gray scales. Further, referring to FIG. 1, the series-connected circuit 2a of the ladder resistors R is arranged in the logic section 2. A plurality of gray scale lines 6 connect the series-connected circuit 2a and the gray scale selection circuit 4.
As shown in FIG. 2, the gray scale selection circuit 4 includes a plurality of switch circuits 7. One end of each switch circuit 7 is connected to a connection node between ladder resistors R (voltage dividing node). The other end of each switch circuit 7 is connected to an input terminal of an operational amplifier 8. In accordance with input signals D0 to D7, which are generated for eight bits, one of the switch circuits 7 is activated. This outputs the desired divisional voltage from the operational amplifier 8 in accordance with the input signals D0 to D7.
With reference to FIG. 3, each switch circuit 7 has a plurality of (eight) series-connected switches 9 corresponding to the input signals D7 to D0. As shown in FIG. 4(a), each switch 9 is a transfer gate, which is configured by an n-channel MOS transistor and a p-channel MOS transistor and which is activated and inactivated by complementary signals D and /D (D0 to D7, and D0/ to D7/). Each switch may be a gate configured only by an n-channel MOS transistor, as shown in FIG. 4(b), or a gate configured only by a p-channel MOS transistor, as shown in FIG. 4(c)
The gray scale selection circuit 4 requires a plurality of switches (gates) 9. This enlarges the chip area. Accordingly, proposals have been made to decrease the number of gates used in the gray scale selection circuit 4 to reduce the chip area (e.g., Japanese Laid-Open Patent Publication No. 9-138670 and Japanese Laid-Open Patent Publication No. 9-258695). More specifically, the publications each describe a voltage dividing circuit, which generates a divisional voltage, into two stages to decrease the number of gray scale voltage selection switches and reduce the chip area.
However, in the technology described in the publications, a buffer for performing impedance conversion is inserted between the first stage of the divisional circuit and the second stage of the divisional circuit. The buffer that is used is an operational amplifier. The employment of the operational amplifier is disadvantageous in that the circuit area increases and the manufacturing cost increases. Further, the operational amplifier has an offset value that produces an output error. Thus, when increasing the gray scales, the potential difference between gray scale voltages decreases and high accuracy becomes necessary. Thus, the application of the above prior art technology is difficult.